FIG. 1 illustrates a typical static random access memory (SRAM) cell 100. A first inverter is formed of an N-channel MOS (NMOS) transistor 102 and P-channel MOS (PMOS) transistor 103 coupled in series between a supply voltage VDD and a ground voltage. A second inverter is formed of an NMOS transistor 104 and a PMOS transistor 105 also coupled in series between the supply voltage VDD and the ground voltage. The gates of transistors 104 and 105 are coupled to a node 106 coupled to the drains of transistors 102 and 103, while the gates of transistors 102 and 103 are coupled to a node 108 coupled to the drains of transistors 104 and 105, such that the inverters form a latch.
The nodes 106 and 108 store complementary voltage states Q and Q, permitting one bit of data to be memorized by the cell. Node 106 is coupled to a bit line BL via a P-channel MOS (PMOS) transistor 110, while node 108 is coupled to a complementary bit line BLB via a PMOS transistor 112. The gates of transistors 110 and 112 are coupled to a word line WL, and are activated by a low signal allowing data to be written to or read from the cell 100.
The circuit 100 has advantage of being relatively quick to access during read and write operations. However, a disadvantage is that, as with all volatile memory cells, the stored data is lost if the supply voltage VDD is removed.
Flash memory is an example of a programmable non-volatile memory. A disadvantage with flash memory is that it is relatively slow to access when compared to the SRAM cell of FIG. 1, and requires a relatively high supply voltage. Furthermore, the Flash technology is difficult to integrate with CMOS, and has relatively low endurance.
In many applications there is a need for a compact programmable memory cell capable of storing non-volatile data, and having increased access speeds.